NVIDIA says Vera CPU is speeding the design of its next-generation AI chips

NVIDIA is using its new Vera CPU inside the electronic-design-automation workflows used to develop future CPUs and GPUs, saying early tests show up to 1.5 times higher performance on selected verification and simulation workloads. The company is working with Cadence and Synopsys to optimise their tools for the processor. The move highlights an often overlooked part of the AI hardware race: faster chips depend not only on accelerator architecture, but also on the ability to test and refine increasingly complicated designs.

Modern processors can take years to move from an architectural idea to manufacturable silicon. Engineers run repeated simulations, formal-verification jobs and regression tests to find corner cases before a design reaches a factory. Some of the most important stages remain heavily dependent on CPU performance even as GPUs and machine learning speed up other parts of the process. Logic simulation and verification often need fast individual cores, efficient memory access and predictable throughput.

NVIDIA says its initial testing used production-class workflows from Cadence and Synopsys. Cadence Jasper, a formal-verification platform, applies proof techniques and machine learning to identify design bugs early. Synopsys VCS simulates and validates complex chip designs before fabrication. In the tests described by NVIDIA, both applications showed up to 1.5 times higher performance on selected workloads while using the same number of cores. The company is also profiling applications and tuning systems with both vendors rather than treating the benchmark as a one-time result.

Vera combines 88 custom NVIDIA Olympus CPU cores with an LPDDR5X memory subsystem and a second-generation Scalable Coherent Fabric. Those components are intended to deliver high per-core performance, memory bandwidth and consistent latency for engineering jobs that mix short, latency-sensitive tasks with large regression runs. Faster individual verification jobs can shorten feedback cycles, while higher overall throughput lets teams test more design alternatives during the same development window.

The significance reaches beyond NVIDIA's internal engineering. Chip designers are under pressure to deliver new accelerator generations while AI demand keeps increasing, and a slower verification loop can delay an entire product schedule. Improvements in the tools used before fabrication may reduce some downstream redesign work, although a benchmark result does not automatically translate into a shorter tape-out schedule. The final effect depends on software integration, system availability and how much of a company's workflow can use the new processor.

NVIDIA is also positioning Vera as part of a continuing CPU roadmap. The company says a future Rosa CPU based on the Rigel core will build on the same strategy of matching each engineering workload with the architecture best suited to it. In this view, GPUs, CPUs and AI models work together throughout the design cycle rather than competing for a single role. NVIDIA is using its own processors to help create later processors, forming a feedback loop between silicon design and system optimisation.

The next evidence will come from broader deployments and results across more tools and design stages. If Vera can deliver consistent gains in real engineering environments, it could help NVIDIA shorten internal development cycles and give CPU performance a more visible role in AI hardware planning. If the gains remain limited to selected tests, the announcement will still show how semiconductor companies are treating design automation as a strategic bottleneck in the race to build more capable AI systems.